1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device having a logical gate including MOS transistors.
2. Description of the Related Art
In recent years, the degrees of integration of semiconductor integrated circuits have been considerably raised, thus resulting in gigabit-class semiconductor memories being provided with several hundred millions of semiconductor devices integrated on one chip thereof and 64 bit microprocessors being provided with millions to ten millions of semiconductor devices integrated on one chip thereof. Each of the foregoing semiconductor memory and the microprocessor of the foregoing type is composed of, as well as a memory cell for storing information, a logical gate for performing logic operations.
FIG. 1A shows a dual-input NAND gate which is a representative logical gate. The logical gate is composed of four elements consisting of two nMOS transistors M1 and M2 and two pMOS transistors M3 and M4. Specifically, the nMOS transistor M1 has a drain connected to output terminal Y, a gate connected to input signal XA, a source connected to node N and a substrate connected to a ground terminal Vss. The nMOS transistor M2 has a drain connected to the node N, a gate connected to input signal XB, a source and a substrate respectively connected to the ground terminal Vss. The pMOS transistor M3 has a drain connected to the output terminal Y, a gate connected to the input signal XA, a source and a substrate respectively connected to power supply terminal Vcc. The pMOS transistor M4 has a drain connected to the output terminal Y, a gate connected to the input signal XB, a source and a substrate respectively connected to the power supply terminal Vcc.
FIG. 1B is a truth table showing the logic of the foregoing logical gate. A definition is performed here that logic 0 is realized when each of input and output signals has ground potential Vss, and logic 1 is realized when the same has supply voltage Vcc. When both of the input signals XA and XB are logic 1, both of the nMOS transistors M1 and M2 are conductive. On the other hand, both of the pMOS transistors M3 and M4 are non-conductive. As a result, output Y is brought to logic 0. If at least either of the input signal XA or the input signal XB is logic 0, the nMOS transistor, to which logic 0 is supplied, is made to be non-conductive. On the other hand, the pMOS transistor, to which logic 0 is supplied, is made to be conductive. As a result, the output Y is made to be logic 1.
FIG. 2A shows a dual-input NOR gate. Similarly to the NAND gate, the foregoing logical gate is composed of four elements consisting of two nMOS transistors M1 and M2 and two pMOS transistors M3 and M4. Specifically, the nMOS transistor M1 has a drain connected to output terminal Y, a gate connected to input signal XA, a source and a substrate respectively connected to ground terminal Vss. The nMOS transistor M2 has a drain connected to the output terminal Y, a gate connected to input signal XB, a source and a substrate respectively connected to the ground terminal Vss. The pMOS transistor M3 has a drain connected to node N, a gate connected to the input signal XA, a source and a substrate respectively connected to power supply terminal Vcc. The pMOS transistor M4 has a drain connected to the output terminal Y, a gate connected to the input signal XB, a source connected to the node N and the substrate connected to the power supply terminal Vcc.
FIG. 2B is a truth table showing the logic of the foregoing logical gate. When both of the input signals XA and XB are logic 0, both of the pMOS transistors M3 and M4 are conductive. On the other hand, both of the nMOS transistors M1 and M2 are non-conductive. As a result, the output Y is logic 1. When at least either of the input signals XA and XB is logic 1, the pMOS transistor, to which logic 1 is supplied, is made to be non-conductive. On the other hand, the nMOS transistor, to which logic 1 is supplied, is made to be conductive. As a result, the output Y is made to be logic 0.
FIG. 3A shows a dual-input AND gate. The foregoing logical gate is composed of 6 elements consisting of four MOS transistors M1, M2, M3 and M4 forming a NAND gate, and a nMOS transistor M5 and a pMOS transistor M6 forming an inverter. Since the NAND gate consisting of the MOS transistors M1 to M4 has the same structure as that shown in FIG. 1A, an explanation of the operation of the NAND gate is omitted. The nMOS transistor M5 has a drain connected to output terminal /Y, a gate connected to output terminal Y of the NAND gate, a source and a substrate respectively connected to ground terminal Vss. The pMOS transistor M6 has a drain connected to the output terminal /Y, a source and a substrate respectively connected to the power supply terminal Vcc.
FIG. 3B is a truth table showing the logic of the foregoing logical gate. Since an inverted signal of the NAND gate is transmitted from the foregoing logical gate, output terminal /Y is made to be logic 1 when both of the input signals XA and XB are logic 1. When at least either of the input signals XA or XB is logic 0, logic 0 is transmitted.
FIG. 4A shows a dual-input OR gate. The foregoing logical gate is composed of 6 elements consisting of four MOS transistors M1, M2, M3 and M4 forming a NOR gate and a nMOS transistor M5 and a pMOS transistor M6 forming an inverter. Since the NOR gate consisting of the MOS transistors M1 to M4 is the same as that shown in FIG. 2A, an explanation of the operation of the NOR gate is omitted. The drain of the nMOS transistor M5 is connected to output terminal /Y, the gate of the same is connected to output terminal Y of the NOR gate, and the source and the substrate are connected to ground terminal Vss. The drain of the pMOS transistor M6 is connected to the output terminal /Y, the gate of the same is connected to the output terminal Y of the NOR gate, and the source and the substrate respectively are connected to the power supply terminal Vcc.
FIG. 4B is a truth table showing the logic of the foregoing logical gate. Since an inverted signal of the NOR gate is transmitted from the foregoing logical gate, the output terminal /Y is made to be logic 0 when both of the input signals XA and XB are logic 0. When at least either of the input signal XA or the input signal XB is logic 1, logic 1 is transmitted.
FIG. 5A shows a dual-input exclusive OR (EXOR) gate. The foregoing logical gate is composed of 10 devices consisting of five nMOS transistors M1, M3, M5, M7 and M9 and five pMOS transistors M2, M4, M6, M8 and M10. The drain of the nMOS transistor M1 is connected to node N1, the gate of the same is connected to input signal XA, the source and the substrate respectively are connected to ground terminal Vss. The drain of the pMOS transistor M2 is connected to node N1, the gate of the same is connected to the input signal XA, the source and the substrate respectively are connected to power supply terminal Vcc. Thus, a CMOS inverter is formed which is composed of the input signal XA and the output terminal N1. Similarly, the nMOS transistor M3 and the pMOS transistor M4 form a CMOS inverter having the input terminal N1 and the output terminal N2. The nMOS transistor M5 and the pMOS transistor M6 form a CMOS inverter having the input signal XB and the output terminal N3.
The nMOS transistor M7 and the pMOS transistor M8 are CMOS transmission gates having drains commonly connected to the node N1 and sources commonly connected to the output terminal Y. Specifically, the gate of the nMOS transistor M7 is connected to the input signal XB and the substrate of the same is connected to the ground terminal Vss. The gate of the pMOS transistor M8 is connected to the node N3 and the substrate of the same is connected to the power supply terminal Vcc. The nMOS transistor M9 and the pMOS transistor M10 are CMOS transmission gates having drains commonly connected to the node N2 and sources commonly connected to the output terminal Y. The gate of the nMOS transistor M9 is connected to the node N3 and the substrate of the same is connected to the ground terminal Vss. The gate of the pMOS transistor M10 is connected to the input signal XB and the substrate of the same is connected to the power supply terminal Vcc.
FIG. 5B is a truth table showing the logic of the foregoing logical gate. When both of the input signals XA and XB are logic 0, the node N1 is logic 1, the node N2 is logic 0 and the node N3 is logic 1. As a result, the transmission gate composed of the MOS transistors M9 and M10 are made to be conductive and the output terminal Y is brought to logic 0 similarly to the node N2. When the input signal XA is logic 0 and the input signal XB is logic 1, the node N1 is logic 1, the node N2 is logic 0 and the node N3 is logic 0. As a result, the transmission gate composed of the MOS transistors M7 and M8 are made to be conductive and the output terminal Y is made to be logic 1 similarly to the node N1. When the input signal XA is logic 1 and XB is logic 0, the node N1 is logic 0, the node N2 is logic 1 and the node N3 is logic 1. As a result, the transmission gate composed of the MOS transistors M9 and M10 are made to be conductive, and the terminal output terminal Y is made to be logic 1 similarly to the node N2. When both of the input signals XA and XB are logic 1, the node N1 is logic 0, the node N2 is logic 1 and the node N3 is logic 0. As a result, the transmission gate composed of the MOS transistors M7 and M8 is made to be conductive, and the output terminal Y is made to be logic 0 similarly to the node N1.
As described above, hitherto, each of the dual-input NAND gate and the NOR gate is composed of four transistors, each of the dual-input AND gate and OR-gate is composed of 6 transistors, and the dual-input EXOR gate is composed of 10 transistors. Therefore, when a large-scale logic circuit consisting of basic gates of the foregoing type is formed, MOS transistors by a number, which is several times the number of the basic gates, are required. Thus, the scale of the logic circuit is enlarged and the area required for the transistor to be disposed is increased, thus resulting in the size of the chip being enlarged unintentionally. If the number of the transistors is increased, the overall capacitance in the chip, which is the total of the gate capacitance, which is the intrinsic capacitance of the MOS transistor, and other parasitic capacitances, is increased. Thus, power consumption for charging and discharging the foregoing capacitances is enlarged.
The degree of integration of an LSI can be raised by fining the device. In a 1G bit DRAM, fine MOS transistors each having a gate length of about 0.15 .mu.m are employed. In a case where the degree of integration is further raised, MOS transistors each having a gate length of 0.1 .mu.m or shorter are employed.
Fine MOS transistors of the foregoing type encounter deterioration in the transistor characteristics due to generation of hot carriers and ruptures of insulating films due to TDDB (Time Dependent Dielectric Breakdown). If the density of impurities in a bulk (a substrate region) or a channel portion is raised to prevent depression of threshold voltage due to shortening of the length of the channel, the breakdown voltage of the source or drain junction deteriorates.
To maintain the reliability of the foregoing fine elements, it is effective to lower the supply voltage. Specifically, the horizontal electric field between the source and the drain is weakened so that generations of hot carriers are prevented. When the vertical electric field between the gate and the bulk is weakened, TDDB is prevented. By lowering the supply voltage, a reverse bias acting on the junction between the source and the bulk and between the drain and the bulk can be lowered. Thus, the deterioration of the breakdown voltage is compensated.
FIG. 6 shows a conventional buffer circuit comprising a three stage CMOS inverter which can be operated with low voltage level. Each of inverters 11, 12 and 13 is formed such that pMOS transistors and nMOS transistors are, in series, inserted between a power supply terminal (Vcc) and a ground terminal (Vss). The power supply terminal Vcc is connected to the substrate of each of the pMOS transistors Mp1, Mp2 and Mp3, while the ground terminal Vss or negative voltage is applied to the substrate of each of the nMOS transistors Mn1, Mn2 and Mn3.
To minimize the delay time in a buffer circuit of the foregoing type, it is preferable that the ratio (fan-out f) of the output capacitance and the input capacitance of each inverter is three. The input capacitance of the inverter 11 is the sum of the gate capacitances of Mp1 and Mn1, while the output capacitance of the same is the sum of the gate capacitances of Mp2 and Mn2. The gate capacitance of the MOS transistor is in proportion to the gate width when the gate length and the thickness of an oxide film are constant. Therefore, assuming that the gate widths of Mp1 and the Mn1 respectively are Wp1 and Wn1, the gate widths of Mp2 and Mn2 are made to be 3.times.Wp1 and 3.times.Wn1, respectively. Similarly, the gate widths of Mp3 and Mn3 are made to be 9.times.Wp1 and 9.times.Wn1, respectively.
The operation of the buffer circuit shown in FIG. 6 will now be described with reference to operation waveforms shown in FIGS. 7A and 7B. Referring to FIGS. 7A and 7B, symbols Iss1, Iss2 and Iss3 represent currents which flow from the corresponding sources of the Mn1, Mn2 and Mn3 to Vss. Symbols Iss represents the sum of Iss1 and Iss3. In a period of time from t0 to t1, input voltage Vin is high, voltage Vn1 of the node N1 and output voltage Vout are low, and the voltage Vn2 of the node N2 is high. At this time, Mn1, Mp2 and Mn3 are made to be conductive, while Mp1, Mn2 and Mp3 are made to be non-conductive. If the absolute values of the threshold voltages of Mp1, Mn2 and Mp3 are sufficiently high, the sub-threshold current is sufficiently small and Vn1 and Vout are made to be Vss and Vn2 is made to be Vcc.
If the level of Vcc has been made to be lowered due to the employed fine MOS transistors, the operating margin of the circuit must be obtained by making the absolute value of the threshold voltage to be smaller than that in a case where the supply voltage is not lowered. If Vcc is 0.5V, the absolute value of the threshold voltage must be lowered to about 0.1V to about 0.2V. If the threshold voltage is low as described above, the sub-threshold current is enlarged to be tens to hundreds of nA. Therefore, Iss1, Iss2 and Iss3 cannot be ignored, thus resulting in that Vn1 and Vout being undesirably made to be higher than Vss. Moreover, Vn2 is made to be lower than Vcc.
When transition of Vin from Vcc to Vss is performed in the period of time from t1 to t2, Mp1 is made to be conductive if Vin has been made to be lower than Vcc-Vtp1 (Vtp1: an absolute value of the threshold voltage of Mp1). Thus, Vn1 is raised. If Vn1 is made to be higher than Vtn2 (Vtn2: threshold voltage of Mn2), Mn2 is made to be conductive and Vn2 is lowered. If Vn2 is made to be lower than Vcc-Vtp3 (Vtp3: absolute value of threshold voltage of Mp3), Mp3 is made to be conductive and Vout is raised. At this time, transitions of Mn1, Mp2 and Mn3 to the non-conductive state are performed.
In a period of time from t2 to t3, Vin is lowered, Vn1 and Vout are raised and Vn2 is lowered. Therefore, Mn1, Mp2 and Mn3 are conductive. If the absolute values of the threshold voltages of Mn1, Mp2 and Mn3 are sufficiently high in the foregoing case, the sub-threshold current is sufficiently small. Thus, the potential Vout of the output is charged to be Vcc. Since the absolute value of the threshold voltage must be lowered if the voltage is low as described above, Vn1 and Vout are undesirably made to be lower than Vcc and Vn2 is raised to a level higher than Vss. Also the standby current is enlarged.
FIG. 8 shows an example of a conventional complementary logical gate corresponding to lowered voltage and comprising MOS transistors. Symbols M3 and M4 represent nMOS transistors having gates to which complementary signals IN and /IN are supplied. Their sources are commonly connected to Vss so that complementary signals OUT and /OUT are transmitted from their drains. A p-type region, which is a substrate, is applied with Vss or negative voltage. Symbols M1 and M2 represent pMOS transistors having gates cross-coupled to OUT and /OUT, the pMOS transistors M1 and M2 having sources commonly connected to Vcc and drains connected to OUT and /OUT. An n-type region, which is a substrate, is connected to Vcc.
The operation of the foregoing logical gate will now be described with timing charts shown in FIGS. 9A and 9B. Input signals IN and /IN are complementary signals having an amplitude between the supply voltage Vcc and the ground voltage Vss. Assumptions are made here that transition of IN from Vcc to Vss and that of /IN from Vss to Vcc have been performed (in a period of time from t1 to t2). Since M3 is turned off and M4 is turned on at this time, OUT is lowered from Vcc to Vss. As a result, M1 is turned on, thus resulting in /OUT being raised from Vss to Vcc so that M2 is turned off. Therefore, outputs OUT and /OUT are inverted complementarily. A similar operation is performed in a case where transition of IN from Vss to Vcc and that of /IN from Vcc to Vss in a period of time from t3 to t4 are performed.
When the logical gate is operated with the low voltage, the threshold voltage of the MOS transistor must be lowered. If the threshold voltage is high, a current for operating the MOS transistor is reduced. In the foregoing case, the switching speed will be lowered. If the supply voltage has been made to be lower than the threshold voltage, the MOS transistor cannot be operated.
If the threshold voltage is lowered, the cutoff characteristic, which is realized when the gate-source voltage has been made to be 0V, deteriorates. Specifically, the sub-threshold current of the MOS transistor is enlarged and the standby current is enlarged. FIG. 9C shows current Icc which flows from Vcc to Vss when a complementary gate is being operated. In a case where the threshold voltage of the MOS transistor is low and the sub-threshold current is large, current Isb unintentionally flows in a standby mode (in a period from time t0 to t1 and that from time t2 to t3) in which transitions of the input signal and the output signal are inhibited and the potential has been defined.
FIG. 10 shows an example of a conventional inverter, which is the simplest logical gate composed of nMOS transistors. The gate of a nMOS transistor M11 is connected to a power supply terminal (Vcc) and the bulk of the same is connected to power source E so that 0V or negative voltage is being applied to a ground terminal (Vss). Reference numeral M11 represents a depletion type nMOS transistor arranged such that threshold voltage Vt realized when voltage E is applied between the bulk and the source is 0V and Vt realized when the voltage of output OUT is V0 is VtL. Input signal IN is supplied to the gate of the nMOS transistor M12 and the bulk of the same is connected to the power source E.
The operation of the foregoing inverter will now be described with reference to timing charts shown in FIGS. 11A to 11C. When IN is Vcc in a period of time from t0 to t1, M12 is in a state where it is turned on. At this time, also M11 is in a state where it is turned on. In a case where M12 has the drive capability considerably superior to that of M11, output OUT is made to be substantially Vss so that standby current Isb' flows. When transition of IN from Vcc to Vss has been performed in a period of time from time t1 to t2, transition of M12 to a state where it is turned off is performed so that output OUT is charged to a high level. If the gate width of M11 is too small at this time, the load capacitance connected to the OUT cannot be changed at high speed. Therefore, the gate width is required to be enlarged to correspond to the load capacitance.
In a standby mode in period of time from time t2 to t3, IN is Vss so that M12 is in a state where it is turned off. If the threshold voltage Vt of M12 is sufficiently high, the leak current (sub-threshold current) in the turned off state is sufficiently small. Thus, OUT is charged to Vcc. If the supply voltage Vcc is lowered due to the employment of fine MOS transistors, the operating margin of the circuit must be obtained by making Vt to be lower than Vcc. If Vcc is 0.5V for example, Vth is required to be lowered to about 0.1V to about 0.2V. The low threshold voltage of the foregoing level causes the sub-threshold current to be enlarged to tens to hundreds of nA. In the foregoing case, the leak current in the turned off state cannot be ignored. As a result, OUT can be charged to an unsatisfactory low level of V0, that is, the level cannot be raised to Vcc. Moreover, standby current Isb flows unintentionally. In a period of time from time t3 to t4, transition of IN from Vss to Vcc is performed so that OUT is raised to substantially Vss.
In general, power consumption P of a logical gate is expressed by P=CVcc.sup.2 f, where C is the sum of a parasitic capacitance and a intrinsic capacitance of the MOS transistor forming the logical gate, Vcc is the supply voltage and f is the operation frequency. Assuming that the operation frequency is constant, the power consumption can be reduced by reducing the capacitor C or by lowering the supply voltage Vcc. The capacitor C can effectively be reduced by decreasing the number of the MOS transistors forming the logical circuit or by reducing the gate width of the transistor. Since power consumption P is in proportion to the square of Vcc, the power consumption can further effectively be reduced by lowering Vcc.
Recently, a pass-transistor logic has attracted attention as a logical gate capable of realizing a complicated logic while necessitating a small number of devices and a simple structure. FIG. 12 shows a dual-input AND and NAND gates each of which is formed by the pass-transistor logic. In the foregoing logical gate, AND logic is formed by two nMOS transistors M1 and M2; and NAND logic is formed by two nMOS transistors M3 and M4 as a pass-transistor network. Moreover, signals Y and /Y appearing at the output nodes N1 and N2 of the pass-transistor network are amplified by a buffer circuit formed by pMOS transistors M5 and M7 and nMOS transistors M6 and M8. To maintain the high level of the output nodes N1 and N2, a latch circuit consisting of two pMOS transistors M9 and M10 is provided.
The source of the nMOS transistor M1 is connected to the node N1, the drain of the same receives signal XA and the gate of the same receives signal XB. The source of the nMOS transistor M2 is connected to the node N2, the drain of the same receives signal XB and the gate of the same receives complementary signal /XB of the signal XB. Definitions are performed that logic 0 is realized when the input and output signals are ground voltage Vss and logic 1 is realized when the same is supply voltage Vcc. When input signal XB is logic 1, nMOS transistor M1 is conductive and nMOS transistor M2 is non-conductive. As a result, the output node N1 has the same logic as that of the signal XA so that the output node N1 has logic 0 when the signal XA is logic 0. When the signal XA is logic 1, the node N1 has logic 1. When the input signal XB is logic 0, the nMOS transistor M1 is non-conductive and the nMOS transistor M2 is conductive. As a result, the output node N1 has the same logic 0 as that of the signal XB.
The source of the nMOS transistor M3 is connected to the node N2, the drain of the same receives the signal /XB and the gate of the same receives the signal /XB. The source of the nMOS transistor M4 is connected to the node N2, the drain of the same receives complementary signal /XA of the signal XA and the gate of the same receives the signal XB. When the input signal XB is logic 1, the nMOS transistor M3 is non-conductive and the nMOS transistor M4 is conductive. As a result, the output node N2 has logic opposite to that of the signal XA so that the output node N2 has logic 1 when XA is logic 0 and has logic 0 when XA is logic 1. If the input signal XB is logic 0, the nMOS transistor M3 is conductive and the nMOS transistor M4 is non-conductive. As a result, the output node N1 has logic 1 which is opposite to that of the signal XB.
Since the signals Y and /Y are input signals passed through the nMOS transistors M1 to M4, their drive compatibilities have deteriorated due to the resistances of the transistors. Assuming that the threshold voltages of the nMOS transistors M1 to M4 are Vt, the outputs each denoting logic 1 from the foregoing transistors are made to be lower than the supply voltage by Vt. Therefore, when the following pass-transistor network is operated in response to the signals Y and /Y, the drive compatibility of the output signal from the pass-transistor further deteriorates. As a result, the operation speed is undesirably lowered and an erroneous operation takes place. Accordingly, the signal Y is inverted and amplified by a CMOS inverter formed by the pMOS transistor M5 and the nMOS transistor M6, while the signal /Y is inverted and amplified by a CMOS inverter formed by the pMOS transistor M7 and the nMOS transistor M8. As a result, an AND output having drive compatibility can be obtained from the output OUT and a NAND output having drive compatibility can be obtained from the output /OUT.
Since the outputs denoting logic 1 from the nodes N1 and N2 are lower than the supply voltage by Vt, the drive compatibility of the nMOS transistor M6 or M7, each having the gate which receives the foregoing output, deteriorates or the cutoff characteristic of the pMOS transistor M5 or M7, each having the gate, which receives the foregoing output, deteriorates. As a result, desired drive compatibility cannot sometimes be obtained or the power consumption is enlarged considerably due to a short-circuit current. Accordingly, the latch circuit composed of a pMOS transistor M9, having a source connected to the supply voltage Vcc, a gate connected to the node N2 and a drain connected to the node N1 and a pMOS transistor M10, having a source connected to Vcc, a gate connected to the node N1 and the drain connected to the node N2, maintains the potentials of the portions of logic 1 of the nodes N1 and N2 at Vcc.
As described above, in the gate circuit composed of the conventional pass-transistor logic, a dual-input AND/NAND gate having drive compatibility is formed by the buffer circuit having four nMOS transistors and two CMOS inverters; and the latch circuit having two pMOS transistors.
To operate the logical gate while maintaining the reliability of the device and even if the supply voltage Vcc has been lowered to prevent electric power consumption, the threshold voltage of the MOS transistor is required to be lowered. If the threshold voltage is high, the drive compatibility of the MOS transistor deteriorates causing the operation speed to be lowered. If the supply voltage is made to be lower than the threshold voltage, the MOS transistor cannot be operated. However, if the threshold voltage is lowered, the cutoff characteristic of the nonconductive transistor deteriorates. Specifically, transistors having the gates, to each of which logic 0 has been supplied, cannot be made non-conductive. In the foregoing case, there is a risk that an erroneous operation of the circuit takes place.
If the wiring capacitance is ignored, the load capacitance of the node N1 is made to be the sum of the gate capacitance of the nMOS transistor M6, the gate capacitance of the pMOS transistor M5, the drain coupling capacitance of the pMOS transistor M9 and the gate capacitance of the pMOS transistor M10. On the other hand, the load capacitance of the node N2 is made to be the sum of the gate capacitance of the nMOS transistor M8, the gate capacitance of the pMOS transistor M7, the drain coupling capacitance of the pMOS transistor M10 and the gate capacitance of the pMOS transistor M9. Therefore, the nodes N1 and N2 are required to drive large capacitances. As a result, the nMOS transistors M1 to M4 forming the pass-transistor network and the pMOS transistors M9 and M10 forming the latch circuit must have gates each having a large width.
To operate the MOS transistors in a state where the supply voltage has been lowered, the threshold voltage is required to be lowered. If the threshold voltage is high, the drive compatibility of the MOS transistor deteriorates. As a result, the operation speed will be lowered. If the supply voltage is lower than the threshold voltage, the MOS transistor cannot be operated. However, if the threshold voltage is lowered, the cutoff characteristic of the MOS transistor deteriorates. Thus, it leads to a fact that an erroneous operation of the circuit takes place. Since a leak current is enlarged in the foregoing case, the power consumption is enlarged unintentionally.
Recently, an invention of a structure has been disclosed in which a body region of MOS transistors formed on a SOI (Silicon On Insulator) substrate is connected to a gate electrode to lower the threshold voltage when the MOS transistor is conductive and to raise the threshold voltage when the same is non-conductive. FIG. 13 shows a nMOS transistor M1 having the foregoing structure.
FIG. 14 shows a result of plotting of voltage V.sub.BS between the body and the source of the nMOS transistor M1, threshold voltage V.sub.TN of the same and current I.sub.BS between the body and the source with respect to voltage V.sub.GS between the gate of the same and the source. Since the gate and the body are connected to each other, V.sub.BS =V.sub.GS. Since the voltage of the body is raised when V.sub.GS has been raised, V.sub.TN is lowered. Since the body of the nMOS transistor is a p-type semiconductor and the source of the same is an n-type semiconductor, a pn junction is formed by the body and the source. If V.sub.GS has been raised to be higher than forward directional voltage V.sub.F (about 0.7V), forward directional current I.sub.BS flows. Therefore, in a case where a semiconductor integrated circuit device comprising a MOS transistor of a type having the foregoing structure is operated with supply voltage higher than V.sub.F, current I.sub.BS flows into the source from the body as well as the current which flows from the drain if V.sub.GS is made to be higher than V.sub.F. In a case where the foregoing semiconductor integrated circuit device is operated with supply voltage lower than V.sub.F, V.sub.GS is sometimes made to be higher than V.sub.F due to noise generated in the circuit or external noise. Since current consumption is enlarged when I.sub.BS flows, the reduction of the power consumption cannot be realized as desired. Since a current, which is not required for the operation of the circuit, flows, an erroneous operation of the circuit takes place and noise is generated. Thus, the reliability of the circuit deteriorates.
If the voltage between the body and the source is forwards biased to a level higher than V.sub.F, a parasitic bipolar transistor is operated, the emitter, the base and the collector of which are the drain, the body and the source, respectively. If the drain voltage is too high, the breakdown voltage of the nMOS transistor encounters deterioration because impact ionization is accelerated in the vicinity of the drain due to electrons injected from the source into the body.
As described above, the conventional logic circuit comprising the MOS transistors encounters the following problems:
(1) Transistors are required by a number which is several times the number of basic gates, thus resulting in the cost of the chip being enlarged when the area of the device is enlarged. Since the power consumption is enlarged as the capacitance in the chip is enlarged, the characteristic of the device deteriorates due to rise of the temperature, the cost of the chip is further enlarged due to employment of a section for performing heat radiation and uses are limited because large electric power is required. PA1 (2) If the voltage is lowered to maintain the reliability of the device and if the threshold voltage is lowered to obtain a margin for the circuit to operate, the current, which flows in the standby mode, is enlarged. As a result, there arises a problem in that the reduction in the power consumption cannot easily be achieved. Another problem arises in that the cutoff characteristic of the MOS transistor deteriorates and thus the circuit erroneously operated. PA1 (3) Since the conventional pass-transistor logic circuit comprises a CMOS inverter which serves as the buffer circuit, the output load of the pass-transistor network is enlarged, thus causing a necessity to arise in that the gate widths of the transistors forming the pass-transistor network and those forming the latch circuit are enlarged. As a result, there arise problems in that the enlargement of the area of the device results in the cost of the chip being enlarged and that the power consumption is enlarged due to enlargement of the capacitance. PA1 (4) The nMOS transistor, in which the gate and the body are connected to each other, has a problem in that a large current flows into a portion between the body and the source if the gate-source voltage exceeds forward directional voltage V.sub.F of the pn junction between the body and the source and, therefore, the power consumption is enlarged excessively. The pMOS transistor, in which the gate and the body are connected to each other, has a problem in that a large current flows between the body and the source if the gate-source voltage is made to be smaller than -V.sub.F and, therefore, the power consumption is enlarged excessively. What is worse, the bipolar transistor consisting of the source, body and the drain is operated, the impact ionization is accelerated in the vicinity of the drain. Thus, there arises a problem in that the breakdown voltage deteriorates. The foregoing problem is critical for nMOS transistors. PA1 (1) a semiconductor integrated circuit device capable of decreasing the number of transistors forming the basic gates, reducing the cost of the chip and reducing power consumption; PA1 (2) a semiconductor integrated circuit device capable of maintaining a margin for the operation of the circuit even if the supply voltage has been lowered and capable of reducing a standby current to be further adaptable to a high speed operation; PA1 (3) a semiconductor integrated circuit device capable of lowering the voltage while having a sufficiently large operation margin without a necessity of lowering the threshold voltage and reducing an output load of a pass-transistor network without deterioration of drive compatibility; and PA1 (4) a semiconductor integrated circuit device capable of preventing flowing an electric body-source current even if the gate-source voltage has exceeded V.sub.F in a case of a nMOS transistor and even if the gate-source voltage has been made to be lower than V.sub.F in a case of a pMOS transistor. PA1 (1) By connecting a nMOS transistor and a resistance element (the resistance element is disposed adjacent to the power source) in series, a dual-input NOR gate or a dual-input NAND gate is formed (see FIG. 18); PA1 (2) By connecting a pMOS transistor and a resistance element in series (the resistance element is disposed adjacent to the ground), a dual-input NOR gate or a dual-input NAND gate is formed (see FIG. 22); PA1 (3) By connecting a pMOS transistor and a nMOS transistor in series, a dual-input NOR gate or a dual-input NAND gate is formed (see FIG. 23); PA1 (4) By connecting a nMOS transistor and a resistance element in series (the resistance element is disposed adjacent to the ground), a dual-input OR gate or a dual-input AND gate is formed (see FIG. 24): PA1 (5) By connecting a pMOS transistor and resistance element in series (the resistance element is disposed adjacent to the power source), a dual-input OR gate or a dual-input AND gate is formed (see FIG. 25); PA1 (6) By connecting a pMOS transistor and a nMOS transistor in series, a dual-input OR gate or a dual-input AND gate is formed (see FIG. 26); PA1 (7) By connecting two nMOS transistors and a resistance element in series (the resistance element is disposed adjacent to the power source), 4-input NAND gate is formed (see FIG. 28A); PA1 (8) By, in series, connecting a resistance element to two pMOS transistors connected in parallel (the resistance element is disposed adjacent to the ground), a 4-input NAND gate is formed (see FIG. 28B); PA1 (9) By, in series, connecting two nMOS transistors connected in series to two pMOS transistors connected in parallel, a 4-input NAND gate is formed (see FIG. 28C); PA1 (10) By, in series, connecting a resistance element to two nMOS transistors connected in parallel (the resistance element is disposed adjacent to the power source), a 4-input NOR gate is formed (see FIG. 29A); PA1 (11) By connecting two pMOS transistors and a resistance element (the resistance element is disposed adjacent to the ground), a 4-input NOR gate is formed (see FIG. 29B); PA1 (12) By, in series connecting two nMOS transistor connected in parallel to two pMOS transistors connected in series, a 4-input NOR gate is formed (see FIG. 29C); PA1 (13) By connecting two nMOS transistors and a resistance element in series (the resistance element is disposed adjacent to the ground), a 4-input AND gate is formed (see FIG. 30A); PA1 (14) By, in series, connecting a resistance element to two pMOS transistors connected in parallel (the resistance element is disposed adjacent to the power source), a 4-input AND gate is formed (see FIG. 30B); PA1 (15) By, in series, connecting two nMOS transistors connected in series to two pMOS transistors connected in parallel, a 4-input AND gate is formed (see FIG. 30C): PA1 (16) By, in series, connecting a resistance element to two nMOS transistors connected in parallel (the resistance element is disposed adjacent to the ground), a 4-input OR gate is formed (see FIG. 31A); PA1 (17) By connecting two pMOS transistors and a resistance in series (the resistance element is disposed adjacent to the power source), a 4-input OR gate is formed (see FIG. 31B); PA1 (18) By, in series, connecting two nMOS transistors connected in parallel and two pMOS transistors connected in series, a 4-input OR gate is formed (FIG. 31C); PA1 (19) By connecting two nMOS transistors and a resistance element in series (the resistance element is disposed adjacent to the power source), 2-rail 2-input EXNOR gate is formed (see FIG. 32A); PA1 (20) By connecting four nMOS transistors in series, a 2-rail 2-input EXNOR gate is formed (see FIG. 32B); PA1 (21) By connecting two nMOS transistors and two pMOS transistors in series, a 2-rail 2-input EXNOR gate is formed (see FIG. 32C); PA1 (22) By, in series, connecting a resistance element to two nMOS transistors connected in parallel (the resistance element is disposed adjacent to the power source), a 2-rail 2-input EXNOR gate is formed (see FIG. 32D); PA1 (23) By using two sets of two nMOS transistors connected in series to commonly connecting respective connection points, a 2-rail 2-input EXNOR gate is formed (see FIG. 32E); PA1 (24) By using two sets of a nMOS transistor and a pMOS transistor connected in series to commonly connect respective connection points, a 2-rail 2-input EXNOR gate is formed (see FIG. 32F); PA1 (25) By connecting two nMOS transistors and a resistance element (the resistance element is disposed adjacent to the ground), a 2-rail 2-input EXOR gate is formed (see FIG. 34A); PA1 (26) By connecting a resistance element to two nMOS transistors connected in parallel (the resistance element is disposed adjacent to the ground), a 2-rail 2-input EXOR gate is formed (see FIG. 34B); PA1 (27) By connecting a resistance element to two nMOS transistors (the resistance element is disposed adjacent to the power source), and by connecting a NOR gate to a gate (a first gate) to which respective transistors are commonly connected, a 2-rail 2-input EXOR gate is formed (see FIG. 34C); and PA1 (28) By connecting a resistance element to two nMOS transistors (the resistance element is disposed adjacent to the power source) and by connecting a NOR gate to a substrate region (a second gate) to which respective transistors are commonly connected, a 2-rail 2-input EXOR gate is formed (see FIG. 34D). PA1 (1) A first delay circuit connected to the gate of the first nMOS transistor to receive the first signal so as to transmit a third signal to the gate of the first nMOS transistor, and a second delay circuit connected to the gate of the second nMOS transistor to receive the second signal so as to transmit a fourth signal to the gate of the second nMOS transistor are further comprised; PA1 (2) The nMOS transistor and the pMOS transistor are formed on the semiconductor substrate formed on an insulating film; PA1 (3) The semiconductor substrates having the nMOS transistor and the pMOS transistor formed thereon are electrically separated from each other; PA1 (4) The first and second input circuits are formed by one nMOS transistor or a plurality of nMOS transistors connected in parallel in such a manner that the substrate region corresponding to the semiconductor substrate is connected to the gate of the one or more nMOS transistors; PA1 (5) The first and second input circuits are formed by one nMOS transistor or a plurality of nMOS transistor connected in parallel in such a manner that a delay circuit is formed between the gate of the one or more nMOS transistors and the substrate region corresponding to the semiconductor substrate; PA1 (6) The substrate regions corresponding to the semiconductor substrate having the MOS transistors of the first and second input circuits are electrically separated from each other; PA1 (7) The first and second input circuits are formed by one nMOS transistor or a plurality of nMOS transistors connected in series in which the substrate region corresponding to the semiconductor substrate is connected to a gate; PA1 (8) The first and second input circuits are formed by one nMOS transistor or a plurality of nMOS transistors connected in series in which a delay circuit is connected between a gate and a substrate region corresponding to the semiconductor substrate; PA1 (9) The first and second input circuits are formed by one nMOS transistor or a plurality of nMOS transistors connected in series in which a substrate region corresponding to the semiconductor substrate is connected to a gate; PA1 (10) The first and second input circuits are formed by one nMOS transistor or a plurality of nMOS transistors connected in series in which a delay circuit is connected between a gate and a substrate region corresponding to the semiconductor substrate; PA1 (11) Each of the MOS transistors is formed on a silicon substrate on an insulating film; and PA1 (12) A third pMOS transistor having a source connected to the power supply terminal, a gate and a substrate region corresponding to the semiconductor substrate, which are connected to the second output node, and a drain for receiving the third signal; and a fourth pMOS transistor having a source connected to the power supply terminal, a gate and a substrate region corresponding to the semiconductor substrate, which are connected to the first output node, and a drain for receiving the fourth signal are further comprised. PA1 (1) The first and second limiter devices are diodes arranged such that output voltage with respect to input voltage is set to a first predetermined voltage higher than the potential of the ground terminal and lower than the potential of the power supply terminal; PA1 (2) The first and second limiter devices are pMOS transistors each having a source for receiving the input voltage, a drain for transmitting the output voltage and a gate to which voltage is applied which is lower than voltage obtained by adding first built in voltage between the source and the substrate region corresponding to the semiconductor substrate to a threshold voltage; PA1 (3) Output voltage of each of the third and fourth limiter devices with respect to input voltage is set to a second predetermined potential which is higher than the potential of the ground terminal and lower than the potential of the power supply terminal; and PA1 (4) The third and fourth limiter devices are nMOS transistors each having a source for receiving the input voltage, a drain for transmitting the output voltage, and a gate to which voltage is applied which is higher than voltage obtained by adding second built in voltage between the source and the substrate region corresponding to the semiconductor substrate to threshold voltage. PA1 (1) The limiter circuit is formed by a second MOS transistor which is different from the first MOS transistor which has a source connected to the substrate region corresponding to the semiconductor substrate, a gate which is applied with first voltage and a drain which is applied with second voltage. PA1 (2) The first MOS transistor and the capacitor are formed in one element region. PA1 (3) The first MOS transistor and the second MOS transistor are formed in one element region.